This lab lays the foundation of modern digital design by first presenting the scripting and hardware description language base for specification of digital systems and interactions with tool flows. The labs are centered on a large design with the focus on rapid design space exploration. The lab exercises culminate with a project design, e.g., implementation of a three-stage RISC-V processor with a register file and caches. The design is mapped to simulation and layout specification.

*Unless taken in a previous term, enrollment in EECS
151/251A is REQUIRED along with lab. If you are out of compliance you will be dropped.*

Phase 1 and 2 seats are open to EECS, CS, and non-EECS COE majors. Remaining seats open during the adjustment period.

Repeat Rules

Course is not repeatable for credit.