This lab covers the design of modern digital systems with Field-Programmable Gate Array (FPGA) platforms. A series of lab exercises provide the background and practice of digital design using a modern FPGA design tool flow. Digital synthesis, partitioning, placement, routing, and simulation tools for FPGAs are covered in detail. The labs exercises culminate with a large design project, e.g., an implementation of a full three-stage RISC-V processor system, with caches, graphics acceleration, and external peripheral components. The design is mapped and demonstrated on an FPGA hardware platform.

*Unless taken in a previous term, enrollment in EECS
151/251A is REQUIRED along with lab. If you are out of compliance you will be dropped.*

Phase 1 and 2 seats are open to EECS, CS, and non-EECS COE majors. Remaining seats open during the adjustment period.

Repeat Rules

Course is not repeatable for credit.