Spring 2025
EECS 151LB 002 - LAB 002
Field-Programmable Gate Array Laboratory
John Wawrzynek
Class #:28918
Units: 2
Instruction Mode:
In-Person Instruction
Offered through
Electrical Engineering and Computer Sciences
Current Enrollment
Total Open Seats:
1
Enrolled: 19
Waitlisted: 0
Capacity: 20
Waitlist Max: 10
No Reserved Seats
Hours & Workload
3 hours of instructional experiences requiring special laboratory equipment and facilities per week, and 3 hours of outside work hours per week.
Other classes by John Wawrzynek
Course Catalog Description
This lab covers the design of modern digital systems with Field-Programmable Gate Array (FPGA) platforms. A series of lab exercises provide the background and practice of digital design using a modern FPGA design tool flow. Digital synthesis, partitioning, placement, routing, and simulation tools for FPGAs are covered in detail. The labs exercises culminate with a large design project, e.g., an implementation of a full three-stage RISC-V processor system, with caches, graphics acceleration, and external peripheral components. The design is mapped and demonstrated on an FPGA hardware platform.
Class Notes
*Unless taken in a previous term, enrollment in EECS
151/251A is REQUIRED along with lab. If you are out of compliance you will be dropped.*
Phase 1 and 2 seats are open to EECS, CS, and non-EECS COE majors. Remaining seats open during the adjustment period.
151/251A is REQUIRED along with lab. If you are out of compliance you will be dropped.*
Phase 1 and 2 seats are open to EECS, CS, and non-EECS COE majors. Remaining seats open during the adjustment period.
Rules & Requirements
Repeat Rules
Course is not repeatable for credit.
Reserved Seats
Current Enrollment
No Reserved Seats
Textbooks & Materials
See class syllabus or https://calstudentstore.berkeley.edu/textbooks for the most current information.
Guide to Open, Free, & Affordable Course Materials
Associated Sections
None